Exploiting Parallelism in Hardware Implementations of the DES

The Data Encryption Standard algorithm has features which may be used to advantage in parallelizing an implementation. The kernel of the algorithm, a single round, may be decomposed into several parallel computations resulting in a structure with minimal delay. These rounds may also be computed in a pipelined parallel structure for operations modes which do not require cryptext feedback. Finally, system I/O may be performed in parallel with the encryption computation for further gain. Although several of these ideas have been discussed before separately, the composite presentation is novel. Comments University of Pennsylvania Department of Computer and Information Science Technical Report NO. MSCIS-93-22. This technical report is available at ScholarlyCommons: http://repository.upenn.edu/cis_reports/460 Exploiting Parallelism In Hardware Implementation of the DES MS-CIS-93-22 DISTRIBUTED SYSTEMS LAB 20 Albert G. Broscius Jonathan M. Smith University of Pennsylvania Scllool of Engineering and Applied Science Computer and Information Science Department Philadelpllia, PA 19104-6389